1. Field
This patent application relates to an output buffer circuit forming a three-state buffer circuit, and more particularly to an output buffer circuit that can be used with a plurality of power voltage sources and without using any high voltage insulated transistors and level shift circuits, and an interface circuit using the output buffer circuit.
2. Description of Related Art
Conventionally, an output buffer circuit includes a high voltage insulated transistor to output a high voltage, for example, 5 Volts (V), and a level shift circuit to convert a gate voltage of a transistor from a predetermined reference voltage to a voltage, for example, 5V, wherein the level shift circuit requires a number of transistors. In FIG. 1, an output buffer circuit 100 is illustrated as such a conventional circuit. The output buffer circuit 100 includes an input circuit 101, a level shift circuit 102, and an output circuit 103, wherein “OE” and “Sin” represent an output enable signal and an input signal, respectively, “VREF”, “VCC,” and “VEE” represent a reference voltage, a constant voltage, and a ground voltage, respectively. The output circuit 103 includes a P-channel type Metal Oxide Semiconductor transistor (PMOS transistor).
However, providing the high voltage insulated transistor and level shift circuit to the output buffer circuit leads to an increase of manufacturing cost and chip-embedded area due to a number of transistors. Furthermore, the high voltage insulated transistor causes delay of risetime of a signal to be output from an output terminal when a low voltage (e.g., 3.3V) is supplied to a source of the high voltage insulated transistor (PMOS transistor)